In general, some semiconductor devices such flash memories may use relatively high voltages to perform erase and/or program operations. Accordingly, high voltage generators may be included in the semiconductor devices to generate high voltages. A high voltage generator may include a plurality of charge pumps which are connected in series. Each of the charge pumps may generate a high voltage using a pumping operation in response to a predetermined oscillation signal. At this time, the oscillation signal may be generated by an internal oscillation circuit included in the semiconductor device. FIG. 1 shows an oscillation circuit used in a conventional semiconductor device. With reference to FIG. 1, the conventional oscillation circuit 100 includes a detection unit 110, a comparator 120, and a latch unit 130.
The detection unit 110 includes a first detector 112 and a second detector 114, which have a same circuit construction. In addition, the detection unit 110 receives first and second feedback signals VF1A and VF2A and the detection unit 110 generates first and second detection signals VD1A and VD2A. The first and second feedback signals VF1A and VF2A are fed-back from a latch unit 130. The first and second detection signals VD1A and VD2A are charged responsive to a voltage level of the first and second feedback signals VF1A and VF2A. Each of detectors 112 and 114 includes a P-MOS transistor (P1A or P2A), two N-MOS transistors (N1A and N2A, or N3A and N4A), and a capacitor (C1A or C2A). The P-MOS transistor (P1A or P2A) is connected in a series between a power voltage VDD and a ground voltage VSS. The P-MOS transistor (P1A or P2A) and one N-MOS transistor (N1A or N3A) are turned on and off responsive to a feedback signal (VF1A or VF2A). Another N-MOS transistor (N2A or N4A) is turned on and off responsive to a reference voltage Vrefa having a constant voltage level.
The comparator unit 120 includes two comparators 122 and 124, which are embodied using respective differential amplifiers. Each of comparators 122 and 124 compares the reference voltage Vrefa with a respective detection signal VD1A and VD2A provided by the detection unit 110 to generate comparison signals VC1A and VC2A.
As shown in FIG. 1, the latch unit 130 may be an SR (set-reset) latch including two NAND gates 132 and 134. Outputs of the SR latch may be first and second feedback signals VF1A and VF2A which are fed-back to the detection unit 110. In addition, the second feedback signal VF2A may be used as the output of oscillation circuit 100 (an oscillation signal OSCA). As is well known to those skilled in the art, outputs of the NAND gates of the SR latch may be complementary with respect to each other. If two inputs of each NAND gate are “0”, two outputs of the SR latch may be fixed to “1”.
FIG. 2 is a waveform illustrating an oscillation signal according to variations of external power in a conventional oscillation circuit. In the conventional oscillation circuit, a power source voltage may dip to a range in which the differential amplifier may be inoperative (A), and a voltage level (an output of each differential amplifier) of first and second comparison signals VC1A and VC2A may have a level of a ground voltage VSS. Accordingly, two outputs of the latch unit 130 embodied by the SR latch may become “0” so that a power voltage VDD of first and second feedback signals VF1A and VF2A (outputs of the latch unit 130) may be fixed to a level of the power voltage VDD. Thus, even if a power of a normal range is provided after power-dipping of the external power source, an output of the oscillation circuit 100 may still be fixed to a level of the power voltage VDD. As a result, oscillation operation may not restart.
Oscillation circuits are disclosed, for example, in Korean Laid-Open Patent Publication No. 2000-0027506 entitled “AN OSCILATOR FOR GENERATING HIGH VOLTAGE OF FALSH MEMORY DEVICE”, the disclosure of which is hereby incorporated herein in its entirety by reference.